Resources

このドキュメントでは、Xilinx VivadoツールでTySOMボードを使用することに焦点を当て、カスタムハードウェアIPコアをプロジェクトに追加できるようにします。標準プロセッサの手が届かないところで、ZynqチップとAldecボードの可能性を示しています。SDxを使用する場合、Xilinx SDxでTySOMボードを使用する方法に関する別のチュートリアルを用意しました。

ALINT-PROのインストールと実行方法を学びます

This video will show you how to install and setup the main ALINT-PRO application as well as additional rule plug-ins. Installation of extra rulesets can be confirmed within the main tool and enabled via the policy editor. For license verification during setup, the license diagnostic tool provides ample information on the current license file and licensed modules.

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

Perspectives are a configured interface which are comprised of different windows and views. When working at different stages of the design flow it can be useful to have different views open, which can be switched to with use of perspectives. Favorites are used to display select tools, macros, or user-defined commands in the interface and different views that are important to have accessible.

ALINT-PRO's Flow Manager window allows managing the design analysis process in a convenient way. This video will show each step of the design flow, going through parse, elaboration, synthesis, constraints, and finally linting. At each step, more information about a project can be obtained. Additionally, each step includes various settings and configurable properties that allow for a highly customized linting process.

A Workspace is comprised of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace.

The Design Flow Manager (DFM) is designed to automate and simplify the design, synthesis, and implementation processes. The interface takes the form of design flowcharts which show the design path in graphical form. Learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to perform each stage of the synthesis and implementation processes.

The HDL Editor available in Riviera-PRO gives flexibility and provides advanced features to speed up the design process and make debugging easier. It provides shortcuts and tools in every stage of designing. Templates are available to use in the HDL Editor which provides basic constructs in various HDL and gives the option to create templates from code that's already written.

Whether one chooses to develop their design in Active-HDL, Riviera-PRO, Quartus, or Vivado, ALINT-PRO can always be used to perform design rule checking via the tool's convert feature. Converting external project files into ALINT-PRO turns the source project files into the equivalent ALINT-PRO workspace and project structure. Once converted, the design is then accessible to all of the solution's linting and rule checking features.

Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries.

The Outline Viewer available in Riviera-PRO digests VHDL code and breaks it down into it's basic components. It will format and display different components of VHDL code and enable filtering and searching for signals and design objects, making large projects easy to navigate.

ALINT-PRO's violation viewer provides a user friendly window for displaying and managing design rule violations. Coupled with automatic report generators, the tool helps not only to identify any violations within your design, but also document them so that they may be corrected and even prevented in later designs. Automatic report generators come in a number of formats, including CSV, PDF, HTML, as well as Quality Reports which provide metrics on how compliant a design is to a given rule set.

The Block Diagram Editor (BDE) is Active-HDL's tool for graphical entry of VHDL, Verilog, and EDIF designs. This is especially useful to those with HDL designs that are largely structural since it is easier to enter descriptions graphically rather than typing hundreds of source code lines. Learn how to create a new block diagram by adding new ports, adding symbols, editing symbols (pin placement, pin names, etc.), connecting symbols with wires/bus, generate HDL code, and how to create a graphical testbench.

Workflow in ALINT-PRO is organized through projects that are grouped into workspaces. A project will contain the set of properties and files, those being your HDL source code and design constraints, to form a single entity that makes up part of your design. Libraries are automatically generated at the local level and correspond to projects within the workspace. Additional libraries can be added through the tool's library export and attach features.