Resources

Managing your simulation datasets, exploring your design hierarchy and design objects. Loading multiple simulation datasets for debugging and comparison.

Riviera-PRO provides powerful tools that can be used for tracing signals during debugging and simulation. The Drivers/Readers and Dataflow tools allow for the user to observe the connectivity of a design through source code or through graphical display. This video will give an idea of how to use the Drivers/Readers viewer and the Dataflow window.

Riviera-PRO provides a powerful debug tool called Plot. Plots are a graphical technique for representing a data set as a graph showing the relationship between two or more variables. It can be a powerful alternative complement to the traditional alphanumeric and waveform-based HDL debugging tools and techniques. This video will demonstrate each of the four different plot styles Riviera-PRO has and will show how to create them.

Riviera-PRO provides users with the Image Viewer/Window tool which can be used to display an image stored in a memory-like simulation object or visualize simulation object values by color. It can be a powerful alternative to the traditional alphanumeric HDL debugging tools and techniques. This video will demonstrate how the Image tool works and the different options that can be used within the Image window.

Saving waveform configuration to a macro file for reuse, creating a copy of a simulation datasets using 'Save waveform snapshot' option.

Riviera-PRO supports UVM up to the most recent version (IEEE 1800.2-2020) and provides a number of powerful tools that can be used to provide an efficient and comprehensive debugging experience for UVM transactions. This video will go over the tools revolving around UVM transactions such as the UVM Graph, UVM Hierarchy, UVM Configuration, Transactions Streams, Call Stack, and Covergroups.

The Xtrace command in Riviera-PRO creates a report with information about unknown values in a simulated model. These values can be X, U, or any other value. Xtrace has the ability to cross-probe with Dataflow to provide a visualization of the simulated model in order to locate the source of the unknown values. This video will demonstrate how to utilize Xtrace with Dataflow to trace and debug signals of unknown values.

Riviera-PRO’s effective and useful Waveform Viewer comes with a number of features that can be used to further enhance the simulation and debugging experience. This video will demonstrate some of the advanced utilities of the Waveform Viewer such as the Splitter, Signal Breakpoints, and cross-probing.

Transactions provide a high-level view into the behavior of an HDL design. This level of abstraction results in faster simulation times and simpler debugging processes. Riviera-PRO provides a number of tools for transaction debugging. This video will demonstrate these tools using a SystemVerilog design.

Transactions provide a high-level view into the behavior of an HDL design. This level of abstraction results in faster simulation times and simpler debugging processes. Riviera-PRO provides a number of tools for transaction debugging. This video will demonstrate these tools using a VHDL design.

X’s, or unknowns, can occur in simulation when hardware behavior is undetermined. These X’s can potentially cause problems in real hardware when unaddressed. Riviera-PRO provides a number of tools capable of finding the causes of unknowns. This video will demonstrate these tools such as Xtrace, Cause Finder, Waveform Viewer, Drivers/Readers, and Dataflow.

Riviera-PRO provides an additional simulation mode called Post Simulation Debug Mode. This advanced feature allows for viewing simulation results after the simulation has finished. Note that in this mode, some debugging tools normally available during simulation are not usable such as Processes, Call Stack, toggling breakpoints, Dataflow, and stepping through code. Additionally, this feature does not check out the simulation features in your Riviera-PRO license. This video will go over how to access the mode, how to set up simulation to get post-simulation data, and what simulation and debugging tools are available in this mode.

Assertions are monitor-like processes that continuously track design activities and report if signals have the right values at the right times. Riviera-PRO provides a number of debugging tools dedicated to making debugging with assertions more robust and user-friendly. This video will cover all the debugging tools you can use for debugging assertions as well as reports that can be generated for post-simulation assertion analysis.

Xilinx Vivado allows the ability to utilize different simulators besides their own. Because of that, the capabilities of Riviera-PRO’s fast and comprehensive simulator are easily accessible when debugging and simulating Vivado projects. This video provides a general overview of how to simulate and debug Vivado projects using Riviera-PRO’s simulator environment.

Take a look at how to use CocoTB with Riviera-PRO. CocoTB is a Co-routine based Co-simulation TestBench environment. It is useful for design reuse and randomized testing using the python scripting language which offers a faster testing phase due to python's ease of use. Enjoy customizability when building your simulation environment that allows you to interact with the Riviera-PRO simulator like triggers for simulation timing or signals. CocoTB is Linux & Windows compatible and has built-in support for Jenkins.

In order to properly use any Aldec software, Aldec provides customers with two types of licenses: node-locked and floating. This video will cover how to determine the license type as well as how to properly install each type of license onto a Windows machine.

Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   

In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented. A case-study using a UVM testbench and Network-on-Chip design is examined to demonstrate the benefits of emulation.