Resources

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency. The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload.  Play webinar   

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. Play webinar   

Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result their products have significantly more undetected bugs. Randomization can be used in many ways, but it is of course also important to know when not to use it. This presentation will show several levels of applying randomization, both with respect to the actual DUT and the randomization functionality available. The main principles shown are tool independent, but the new UVVM randomization functionality will be used as examples, thus also giving you a kick start using this great tool. Play webinar   

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench. Unfortunately, not many designers are applying functional coverage, and maybe part of the reason for that is the complexity surrounding previous solutions to this functionality. This presentation will show you how it works and how easy it is to get started with this new functionality in UVVM. The presentation will also explain and show the usage of Specification Coverage aka Requirement Coverage, which is a feature to track that all your specification requirements have been covered. Many of us are already familiar with Code Coverage since it’s very easy to use, but some important issues will be presented. Play webinar   

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. This first webinar of a two-part “Fast Track” series is designed to help functional verification engineers get up to speed quickly with Design Management and Design Entry in Riviera-PRO. Includes tips and tricks to enable easier debugging of designs. Also covers how to run Simulations and handling waveforms. Play webinar   

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. This second webinar of a two-part “Fast Track” series is designed to help functional verification engineers get up to speed quickly. In this webinar, you’ll learn about more debugging tips and we’ll also cover Tracing Logic and how to run code coverage in Riviera-PRO. We’ll also take a look at Plots - a new way of analyzing results.  Play webinar   

In the latest release of Open-Source VHDL Verification Methodology (OSVVM), you'll find an API that allows OSVVM Functional Coverage to be recorded within a simulator. Aldec pioneered this interface and has integrated it within their simulators.
OSVVM currently provides VHDL testbenches with Functional Coverage, Intelligent Coverage, and constrained random testing methods. Using this interface brings SystemVerilog like Metric Driven test capability to VHDL.
OSVVM architect and VHDL trainer, JIm Lewis, together with Aldec Software Product Manager, Radek Nawrot, will demonstrate how to add this capability to your VHDL testbench. Play webinar   

ALINT-PRO provides powerful means for static analysis and validation of clock domain crossings(CDC). It extracts and validates clock trees, and clock domains, applying topological pattern-matching methods to validate the correctness of design structures on the clock domain boundaries. However, static CDC verification has to be augmented with the dynamic CDC verification to ensure the absence of CDC-related issues. For this purpose, ALINT-PRO provides assertion-generation engines, allowing designers to enhance their functional verification with CDC checking code. The webinar presents the complete clock domain crossing verification methodology, from static verification with ALINT-PRO up to dynamic verification with Riviera-PRO. It includes a number of design examples, for different synchronizer types. Also, the webinar includes a short introduction to Assertion-Based Verification using SystemVerilog Assertions (SVA). Play webinar   

In this webinar, Chris Higgs of Potential Ventures will demonstrate what is arguably the most productive RTL development flow in the world. By tightly coupling the hardware and software elements into an engineered flow, a rapid and agile approach to FPGA development becomes possible. Taking the best of open and closed source tools, Potential Ventures have created a flow that stands up to the rigorous demands of the cutting edge financial services sector where project times are measured in days and weeks rather than months and years. The webinar will cover all aspects of RTL development including verification, regressions, co-simulation of hardware and software, interactive debug tools, documentation, metric tracking and more. Play webinar   

Learn how to debug your code in Riviera-PRO

Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation. As a result, HDL simulations are becoming excessive and they have become the primary bottleneck when it comes to verification. In this paper we will describe a solution that can accelerate HDL simulation for the system FPGA design that includes the custom logic and reused IP Cores where the testbench executes in the simulator and the synthesizable parts of the design is implemented in a Microchip FPGA board.