FPGA DESIGN & SIMULATION
Active-HDL™
A Windows-based integrated FPGA design creation and simulation environment for team-based development.
CAPABILITIES
Designed for productive verification.
Integrated IDE
Design entry, HDL editing, project management and simulation in one environment.
Mixed-language simulation
Verify VHDL, Verilog and SystemVerilog designs in integrated FPGA workflows.
Graphical design entry
Schematic, block and state-machine oriented design tools complement HDL development.
Vendor flow integration
Coordinate design, synthesis and implementation workflows with FPGA vendor tools.