ADVANCED VERIFICATION
Riviera-PRO™
A high-performance simulation and verification environment for complex FPGA and SoC designs.
CAPABILITIES
Designed for productive verification.
Mixed-language simulation
VHDL, Verilog/SystemVerilog and system-level verification workflows.
Modern methodologies
Support for reusable verification approaches including UVM and open-source methodologies.
Advanced debug
Waveform, dataflow, coverage and post-simulation analysis for faster root-cause investigation.
HW/SW co-verification
Connect programmable logic verification with processor and software models for SoC workflows.