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Multi-FPGA Partitioning on AWS Cloud

Due to the size of today’s SoC designs, the prototyping boards must contain multiple, large FPGA devices that are scalable (or expandable). Selecting the appropriate FPGA prototyping board and design partitioning solutions are among the challenges many teams are facing today. Not only the design has to be split into blocks so that each of them matches one FPGA, but also the user has to arrange interconnections between them using physical I/Os and traces available on the board.

HES-DVM Proto Key Features & Benefits

Fast-track setup for multi-FPGA prototyping
Guided partitioning using design structure model and top-down strategy
Instance logic replication in many partitions for clocking modules
Monitoring utilized logic resources and interconnections
Dry run and “what if” impact analysis to simulate many partition configurations
Automatic conversion of gated clocks and netlist optimization
Clock domain crossing analyzer and timing constraints editor
Support for Aldec HES and third party custom boards
Board-level connecting resources awareness, global clocks and traces, LVDS, single-ended
Automatic insertion of Inter-Chip-Connection (ICC) buses