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Using Plots for HDL Debugging

Using Plots for HDL Debugging

A Powerful Alternative to Traditional Waveforms

Mariusz Grabowski, FPGA Design and Verification Engineer

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The most commonly used approach to analyzing objects in an HDL design is based on well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and many others.

With the release of Riviera-PRO 2013.02, Aldec introduced the Plot window, a new solution for a graph-based analysis of HDL objects and correlations between them. The Plot window enables efficient visualization of large data sets, as well as the ability to visualize and analyze relations between any objects within your design with no additional programming required.

Riviera-PRO Plot Window_QAM_tx_noise_jitter-01_small

To learn more about practical applications for Plot, see a related whitepaper, Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms.

Tags:VHDL,Verilog,SystemVerilog,Riviera-PRO

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

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