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Shaping the Future of ASIC/FPGA DSP Design Flow

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Mariusz Grabowski, FPGA Design and Verification Engineer
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Aldec is conducting a brief survey through April 30, 2013, to better address the challenges and requirements faced by DSP designers in the field.
As a thank you, a random drawing will be held among survey participants to receive a $100 Amazon giftcard.

Survey has ended.

Winner to be notified by email.

Tags:Riviera-PRO

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

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