Do you really need FPGA Design Management?

Absolutely, you do. Most of FPGA design today involves FPGAs from multiple vendors, third party IPs and blocks from legacy design. Design reuse also has become a more critical element given the ever decreasing window for time-to-market. When was the last time you saw single engineer handling entire FPGA design project? It takes a team of engineers to manage today’s FPGA designs. Managing hundreds of files team-wide that involves multiple tools at different stages of design is no easy task.

Active-HDL has been predominantly serving FPGA design market for sixteen years now by constantly adapting to changing demands within the FPGA design domain. The latest version, recently released Active-HDL 9.3, delivers solid FPGA design management tools that bring unified solutions to FPGA design teams.

FPGA Design Structure

The Design Structure feature in Active-HDL provides flexible file management for FPGA design projects. It allows engineers to maintain and adhere to a common design structure that can be used across an entire team. It enables users to create their own design directory that is compatible with other synthesis and implementation tools. Once the flexible directory structure has been created by user – it organizes and maintains the design directory structure by automatically grouping same type of files.

Design Settings – Load time

Load time settings in Active-HDL allow users to set one-time settings when they open FPGA design in Active-HDL. Usually when engineers open FPGA projects in the tool they have to perform certain operation manually, such as launch tool in specific directory, update local variables, set parameters for script engine or execute design specific macros. Imagine if all of these operations could be defined in a script that will automatically execute when the tool is launched. Active-HDL 9.3 allows users to execute start up script that can perform load time settings for FPGA project without manual intervention.

Design Settings – Run time

During the simulation, engineers tweak different settings according their requirements. For example, if you are running a regression then you typically turn off all the debugging settings of simulator to get highest performance. On the other side, if you want to collect the code coverage data, it requires setting coverage options in tool settings. The only problem with this approach is that switching between the settings is time consuming and error prone. Active-HDL allows engineers to use global settings file that can be prepared for running simulation in optimized, debug or coverage mode. Once this global settings file is loaded in tool, all the settings are locked which prevents changing the settings accidentally. These global settings files can be easily shared within team to make sure some settings are consistently applied across the team – such as language standard for compiling VHDL or Verilog code.

For more on the latest release of Active-HDL, you may wish to view our recent press release, Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL™.