Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications FPGA Design Verification in a Nutshell FPGA Design Verification (Planning) in a Nutshell Before wading into this topic, I’d like to state why I felt compelled to write about FPGA design verification. I recently presented a very well attended three-part webinar series, during which many attendees asked for book recommendations.... Tags:ASIC,Coverage,Design,Functional Verification,Debugging,Documentation,Digital,SoC,Verification,Verilog,VHDL Like(0) Comments (0) Read more Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Qualified Zynq SoC Dev Board for IoT Greengrass Everyday there are new devices appearing in homes, offices, hospitals, factories and thousands of other places that are part of the Internet-of-Things (IoT). Clearly, they need to be connected to the internet and there is a need for a huge amount of raw data to be collected... Tags:Design,Digital,Embedded,FPGA,SoC,Xilinx Like(2) Comments (0) Read more What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? Bird’s eye view definition, HW/SW setup and implementation algorithms Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable... Tags:Aceleration,ARM,Embedded,FPGA,Hardware,HDL,Prototyping,Validation,Verification,Verilog,Design,Digital,SoC,Xilinx,Zynq Like(1) Comments (0) Read more How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA A must for high-traffic network A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory... Tags:Aceleration,Design,Digital,Embedded,Emulation,FPGA,Hardware,Industrial,Prototyping,SoC,Xilinx Like(1) Comments (0) Read more Zynq-based Embedded Development Kit for University Programs Cost-effective solution for HW/SW development projects Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises.... Tags:Co-simulation,Embedded,FPGA,HDL,Prototyping,Simulation,SoC,university,Xilinx,Design,Digital Like(1) Comments (0) Read more Transitioning to Advanced Verification Techniques for FPGAs – Catch-22? A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is... Tags:FPGA,Randomization,Verification,Coverage,Digital,IP,Simulation,Verilog,VHDL Like(2) Comments (0) Read more Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design Guest Blog with John Zuk from Tanner EDA Aldec Product Manager, Dmitry Melnik, recently shared a blog update on Verilog-AMS & Multi-Level Simulation. Within the many inquiries he mentions, we noted a consistent theme... Tags:Analog,Digital,Mixed-signal,Simulation Like(2) Comments (0) Read more Verilog-AMS & Multi-Level Simulation Aldec and Tanner EDA Bridge Digital and Analog Design Flows It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2),... Tags:Analog,Digital,Mixed-signal,Simulation Like(1) Comments (0) Read more 90’s Kid Active-HDL Celebrates Sweet 16 Serving FPGA Designers as the tool of choice since, like, forever As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997.... Tags:Assertions,Co-simulation,Coverage,Debugging,Design,Digital,Documentation,FPGA,HDL,IEEE,Matlab,OS-VVM,Simulation,standards,university,Verification,Verilog,VHDL,Xilinx Like(2) Comments (2) Read more
