Aldec Design and Verification Blog

FPGA Design Verification (Planning) in a Nutshell Before wading into this topic, I’d like to state why I felt compelled to write about FPGA design verification. I recently presented a very well attended three-part webinar series, during which many attendees asked for book recommendations....

In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?...

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,...

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

Are you a requirements engineer but your main goal is to provide well organized documentation? Do you have a great knowledge about the industry, business analysis and systems but you are struggling with the shape and look of your documentation?...

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....