Event Details View All Recorded Events Date Event Type 場所 Action Oct 10, 2024 The Development and Evolution of Verilog & SystemVerilog (US) Time: 11:00 AM - 12:00 PM (PST) Abstract SystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities, constrained random testing (CRT), and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today. Cliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog, why the features were added, and the origins of many of those features. Agenda: Verilog HDL and Its Ancestors and Descendants (reference paper) Brief History of Verilog & SystemVerilog HILO, Verilog, C, PLI SDF, Synthesis, VHDL, VPI Superlog, IHDL (Intel), SystemC, Vera OOP, e-Specman, SystemVerilog, C++ OVL, PSL, SVA OVM / UVM history Simulation & Functional Coverage Q&A Presenter BIO Clifford E. Cummings, Vice President of Training at Paradigm Works and Founder of Sunburst DesignCliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog, UVM, CDC and synthesis training classes. Cliff has 42 years of ASIC, FPGA and system design experience and 32 years of combined Verilog, SystemVerilog, UVM verification, synthesis, and methodology training experience. Cliff has taught expert Verilog, SystemVerilog, Design Synthesis, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics. Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University. ウェブセミナー Online More Info
