Aldec to offer DAC Technical Sessions Live Online

In this webinar we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator.  The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate.  This enables tests to be moved seamlessly from simulation to the accelerator and back again

By tightly coupling the hardware and software elements into an engineered flow, a rapid and agile approach to FPGA development becomes possible. Taking the best of open and closed source tools, Potential Ventures has created a flow that stands up to the rigorous demands of the cutting edge financial services sector where project times are measured in days and weeks rather than months and years.  The webinar will cover all aspects of RTL development including verification, regressions, co-simulation of hardware and software, interactive debug tools, documentation, metric tracking and more.

In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages.

In 2015, Open Source VHDL Verification Methodology (OSVVM) added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06). With this expanded capability, this presentation takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling.