Say Hi To Hybrid: ARM Fast Models meet Aldec Emulation

by Doug Amos

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs.

First-rate work by the standards body Accellera and the Open SystemC Initiative (OSCI) has given us all Transaction-Level Modeling, or TLM. TLM has enabled us to create a virtual platform of a CPU sub-system, trading off accuracy for speed in order to provide an early target to test software. In the early days, a common obstacle to realizing such virtual platforms was the availability of SystemC models for various components, for example, a new CPU. If none was available then we would lose time generating a trustworthy model, eroding the benefit of early software test.

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