Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal

Image data resolution is constantly growing in different applications and 4K UltraHD resolution is a standard nowadays. We will demonstrate that Aldec TySOM board which based on Xilinx Zynq FPGA can be successfully used in application and FPGA chip can accelerate functions and algorithms to achieve high performance.

Object detection by a Neural Network is a hot topic nowadays in many fields such as automotive or industrial. Accurate and fast detection and classification is required. These requirements can be fulfilled with system based on FPGA accelerated SoC chips such as Xilinx Zynq. In this presentation we will demonstrate how to utilize Aldec TySOM board for object detection and recognition application.

Hardware-Software co-design and co-verification are indispensable in any kind of SoC design today. Fast and accurate hybrid emulation platform can be built using ARM Hardware Model provided by Xilinx Zynq MPSoC. We will demonstrate how to connect Xilinx Zynq MPSoC and its ARM Cortex A53/R5 processors with the largest Xilinx UltraSCALE US440 FPGA on HES emulation board.

Multi-FPGA partitioning has always been a challenge due to limited number of FPGA I/Os and FPGA-specific clocking tree. Aldec provides HES-DVM Prototyping toolbox that automates design partitioning for multiple FPGAs and integrates ultra-fast HES Proto-AXI host bridge. This year we will demonstrate the new features and improvements that include: Automatic Partitions, Connections, Routing and third-party FPGA boards support.

Aldec and Silvaco continue their efforts to provide robust mixed-signal solution based on high-performance tools such as Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit Simulator. The demo will show mixed-signal simulation and debug capabilities. We will show how the digital and analog domains can communicate and how user can obtain results of Verilog-AMS and Verilog-D co-simulation in Riviera-PRO user interface. Users can view the co-simulation results using Riviera-PRO Advanced Waveform Viewer and debug using Riviera-PRO debugging features such as X-trace, Advanced Data-flow, Code Coverage Collector.

(1) Today's FPGA SoC embedded designs present new verification challenges for both software and hardware engineers. Aldec provides a HW/SW co-simulation approach based on open-source QEMU that can be run together with Verilog-AMS Slivaco SmartSpice co-simulation. Demo will show how to prepare and simulate pulse-width modulation (PWM) module with analog output. Simulation flow combines Riviera-PRO Advanced Verification Platform, Open-Source QEMU and SmartSpice Parallel SPICE.

(2) The world is analog in nature and since electronic devices often work relaying on data gathered by sensors, a system designer is commonly faced with the challenge of integrating digital and analog circuits into a single SoC. Therefore, the ability to efficiently simulate mixed-signal systems becomes essential. Aldec together with Silvaco provide a high-performance mixed-signal solution using Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit simulator. The demo will show simulation and debug capabilities for a smart sensor design. The design will include Verilog and Verilog-AMS modules as well as SPICE netlists and hardware emulation using open-source QEMU.

The increasing number of registers in complex designs becomes a challenge for modeling and verification. Any change in register definition should be automatically propagated to software and hardware engineers to reduce the costs and time involved. The Aldec Register Generator tool allows to create the RTL model for hardware designers, UVM model for verification engineers, C header for software designers and a memory map documentation for users. This presentation will show how to prepare an RTL register model, C definition header and HTML documentation from an IP-XACT or CSV description.

The world is analog in nature and since electronic devices often work relaying on data gathered by sensors, a system designer is commonly faced with the challange of integrating digital and analog circuits into a single SoC. Therefore the ability to efficiently simulate mixed-signal systems becomes essential. Aldec together with Silvaco provide a high-performance mixed-signal solution using Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit simulator. The demo will show simulation and debug capabilities for a smart sensor design. The design will include Verilog and Verilog-AMS modules as well as SPICE netlists and hardware emulation using open-source QEMU.

UVM is a very beneficial methodology when you are verifying large designs, but it also comes with added complexity. In this presentation we are going to take a look at various debug features and tools we have in Riviera-PRO that can make UVM code debug, a much easier process. We will take an in-depth dive into the UVM Toolbox, UVM Graph and other UVM features that will help navigate through the UVM environment and help with finding issues quickly and more efficiently.