DO-254 Verilog / VHDLルール・ライブラリCategory : デザイン・ルール・チェックSet of rules that should be used to improve design compliance with DO-254. It combines knowledge of Aldec’s DO-254 clients and in-house experts. Covered areas include proper signal assignments, clocks/resets issues, correct instantiations, handling of race conditions and mismatched bit widths.
