White Papers

Abstract: This paper presents a new approach in domain of high level digital circuits simulation and modeling that benefits from high level mathematical environment delivered by MATLAB. It allows to integrate design process and directly verify obtained results with mathematical formulas or complex operations that are not available in standard HDL languages. A part of HDL code can be placed for verification purposes inside the advanced mathematical model or can execute complex calculation. Paper presents problems that are introduced by hybrid simulation and modeling environment concerning data representation, simulation process and optimal performance.

Abstract: This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.

Abstract: Modern ASIC and FPGA designs can usually be treated as complete systems, not just electronic circuits. Design and verification of those systems typically requires the use of transaction-level descriptions, so enhanced support for transactions in verification tools is critical. This paper describes basic transaction related terms and the new transaction recording and visualization solution available in Riviera-PRO™ simulator.

If you are new to DO-254, this white paper can serve as your starting point as you educate yourself with the guidance and regulation. This white paper provides an overview of RTCA/DO-254 purpose, scope and processes, and as well as description of Aldec’s specialized tools for DO-254 targeting DAL A and B PLDs.

Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE.

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & V activities more efficiently.

Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.

Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly.

シミュレーションと論理合成のミスマッチの問題は、物理デバイスの誤動作を引き起こす可能性があります。RTLシミュレーションで機能的に完璧であっても、物理的な実装で重大なデザインバグが含まれている可能性があります。RTLリントは、シミュレーションと論理合成のミスマッチ問題を特定して修正する唯一の方法です。本紙では、シミュレーションから論理合成への典型的なミスマッチ問題を簡単な例で示します。 記載されている問題ごとに、リントチェックで確認され、説明されます。

Abstract: Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

SCE-MI 2の3つのユースモデル（マクロベース、ファンクションベース、パイプベース）について。その違い、ユースケース、推奨について

This whitepaper describes how to use Aldec TySOM board as an IoT gateway and build the scalable network with the usage of Amazon AWS Cloud service.

Abstract: Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.

Abstract: This White Paper points out the most significant issues which can be encountered during DO-254 compliant verification process of FPGA designs. It proposes the methods of saving development time during the functional verification process by reusing the work done during RTL simulation for in-hardware at-speed testing in target FPGA devices, which assures a high visibility of results and good traceability of requirements.

Abstract: The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Abstract: Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to be able to meet all those requirements a new approach to the design process is required.

SystemVerilog interfaces offer some very interesting features for both hardware designers and verification engineers. Unfortunately, they are also one of the most misunderstood SV constructs. This document tries to explain interfaces, paying special attention to the virtual interface concept used in popular UVM library.

Abstract: The Aldec DO-254 Compliance Tool Set (CTS) provides support for the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED80) Chapter 11.4 “Tool Assessment and Qualification Process”. Aldec provides support for assessment and qualification of the design and verification tools used in the design of complex electronic hardware such as FPGA, PLD and ASIC devices.

Abstract: Typical ASIC front-end and back-end implementation process involves HDL simulation as a method of verifying design netlist functionality at each stage of the flow. Although HDL simulation is considered accurate it suffers from very low execution speed.Aldec provides the DVM software that allows reusing your existing FPGA prototyping board as a platform for hardware acceleration of HDL simulation.