Multimedia

A Workspace is comprised of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace.

The Design Flow Manager (DFM) is designed to automate and simplify the design, synthesis, and implementation processes. The interface takes the form of design flowcharts which show the design path in graphical form. Learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to perform each stage of the synthesis and implementation processes.

Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries.

The Block Diagram Editor (BDE) is Active-HDL's tool for graphical entry of VHDL, Verilog, and EDIF designs. This is especially useful to those with HDL designs that are largely structural since it is easier to enter descriptions graphically rather than typing hundreds of source code lines. Learn how to create a new block diagram by adding new ports, adding symbols, editing symbols (pin placement, pin names, etc.), connecting symbols with wires/bus, generate HDL code, and how to create a graphical testbench.

Learn how to create a new Finite State Machine (FSM), define ports, add new states, transitions, actions, and conditions; add multiple state machines, generate HDL code, generate a testbench, and run a simulation to trace over the transitions to observe the functionality of the state machine.

The HDL Editor is a text editor for editing HDL source code. It contains features such as keyword coloring (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), recording/playing actions, bookmarks, hyperlinks to files, creating structure groups, breakpoints, autoformat/smart indentation, etc. Learn how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file.

Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts.

One of the newest features implemented into Active-HDL 13.1, Spec-TRACER is a tool that allows capturing traceability data specified in miscellaneous files and storing it in the database file for review, analysis, and reporting purposes. Learn how to access Spec-TRACER, configure Spec-TRACER settings, and generate and understand the Spec-TRACER traceability reports.

The Code2Graphics™ converter is a tool designed for automatic translation of VHDL or Verilog/SystemVerilog source code into Active-HDL block and state diagrams. It analyzes VHDL, Verilog, or EDIF source files and generates one or more block diagram files depending on the number of design entities, modules, or cells found in the analyzed file. This video will show how to use Code2Graphics™ to create block diagrams and state diagrams.

Active-HDL starting with version 9.2 (latest release being 13.1) , instead of source files being automatically saved to the "src" folder, users can customize the design structure for more flexible file management. Users can specify the folder name or path to store a specific file, e.g. HDL files in an HDL folder, BDE files in a BDE folder, and so on. Learn how to customize the design structure, edit/copy/share the design structure configuration file, and convert existing designs to the new structure.

Active-HDL can be run in the batch mode, that is, without using the graphical user interface (GUI). Active-HDL batch mode is referred to as VSimSA or a stand-alone simulator. The batch mode allows running a comprehensive processing of a design or a set of designs. This video will cover how to access both Interactive Mode and Batch Mode as well as demonstrating some basic commands in the VSimSA shell and OS shell to set libraries, compile files, and run simulation.

Active-HDL offers the design rule checking capabilities of ALINT-PRO directly within the tool through unit linting. Running the feature within the design tool's GUI will perform design checks according to the generated ALINT-PRO project, and those violations will be displayed in Active-HDL's console and HDL editor in the form of various warnings and messages. Modification of a design's policy is facilitated through additional context menu items within the Design Browser, which allows launching of ALINT-PRO into the relevant views for modifying policy or waivers.

Active-HDL provides debugging windows such as the Console, Breakpoints, Watch, Process, Call Stack, and List Viewer. Learn how to utilize the features of each window and how to use the windows to debug your designs.

Advanced Dataflow allows designers to explore the connectivity of an active design and analyze the dataflow among instances, concurrent statements, signals, nets, and registers during simulation. There are three display modes to help trace events propagating through the entire project: Hierarchical, Flat, and Gray. Learn how to enable settings to generate data for the Advanced Dataflow window, how to add/view modules in the Advanced Dataflow window, how to utilize context menus within the window (expand net to readers, expand net to drivers, etc.), and how to switch display modes.

XTrace allows users to detect and report unknown values (e.g. X, W, U, etc.) when they first appear, and before they are propagated through a design. Learn how to enable XTrace, set XTrace options, and view signals that contain unknown values.

The Accelerated Waveform Viewer is a high performance tool dedicated to reading and graphically presenting simulation data. Learn how to utilize advanced operations such as zooming, signal manipulations, cursors, measurements, bookmarks, browsing modes, and aliases.

Active-HDL’s Assertion Viewer allows the user to view two types of PSL and SystemVerilog objects during simulation: assert statements and cover statements. The viewer provides useful statistics about these objects in an easily accessible manner. This video provides an overview on how to access and use the Assertion Viewer window.

Active-HDL provides additional simulation modes, including one called Post Simulation Debug Mode. This advanced feature allows for viewing simulation results after the simulation has finished. Note that in this mode, some debugging tools normally available during simulation are not usable such as toggling breakpoints, using Dataflow, and stepping through code. Additionally, this feature does not check out the simulation features in your Active-HDL license, but instead checks out the Post Simulation Debug license feature. This video will go over how to access the mode, how to set up simulation settings to get post-simulation data, and what simulation and debugging tools are available in this mode.

Code coverage is a useful source of metric, that analyzes code execution and can help us determine the completeness of the verification effort. It helps us identify corner cases that may not be executed in your design. Code Coverage analysis tools offered by Active-HDL can provide several different types of information related to the verification process of your design.

Active-HDL provides a number of coverage analysis tools to further enhance verification quality of HDL code. Coverage analysis uses ACDB (Aldec Coverage Database) as a unified format of storing different types of coverage data. This video will go into more detail on one of the Code Coverage options: FSM Coverage. FSM Coverage enables users to determine which states and transitions in the state machine diagram have been executed during simulation. To collect the FSM Coverage statistics, the HDL design code has to include SystemVerilog or Aldec proprietary pragmas indicating which constructs represent components of the state machine. The pragmas used in the HDL code are included in additional lines of comments and interpreted by the coverage engine. The FSM Coverage statistics can be stored in the Aldec Coverage Database (ACDB) files and presented in a textual or HTML report along with OSVVM Functional Coverage providing complete structural coverage and functional coverage with test results merging, ranking and analysis.