How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM In this video, Farhad Fallah from Aldec company provides a deep dive into automatic multi FPGA partitioning features of HES DVM tool. You'll learn how to use HES DVM on AWS cloud to partition any ASIC design into multi FPGAs automatically which takes a lot of time for the verification engineers. Using the FPGA resources efficiently is a challenging problem in multi FPGA prototyping. The lack of enough I/O pins on FPGAs to fit today's complex SoC designs have made the prototyping process very time-consuming and costly for ASIC design companies. Making this process automated could save a lot of engineering costs for such projects.
