Play Webinar

Title: Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs

Description: Presenter: Sergei Zaychenko, Aldec Software Product Manager

Noise reduction is a key trend in currently available Clock Domain Crossing (CDC) Verification solutions. Most CDC tools on the market are unable to extract clocking and reset structures that match the original designer's intent. The designs often contain hundreds of vendor-specific blocks and 3rd-party IPs with unclear clock/reset relations. The timing of external interfaces might not be clearly defined, affecting the CDC results. Multiple clock modes, false paths and custom in-house synchronizers are not making CDC analysis any easier.

A user must typically go through several rounds of tool configuration, policy adjustments, clock/reset constraints refinements, description of timing intent for the black boxes. Bringing the focus to concrete configuration/constraint issues is challenging when forced to browse through thousands of violation messages and full schematics. Much time and effort might be lost on cleaning the configuration through printed CDC end-results, instead of keeping initial focus on correct control structures. In additional, an incorrect/incomplete configuration often leads to poor CDC tool performance.

In this webinar, learn how a seamless, phased-based CDC debugging methodology can reduce overall CDC signoff time.

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