Play WebinarTitle: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVMDescription: Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. This webinar is a guided walk-through of the OSVVM verification framework and transactions provided by OSVVM models. OSVVM's transaction based testbench approach is the current evolution of the approach taught by SynthWorks' for 20+ years. Looking at its block diagram, you will notice that its architecture looks similar to SystemVerilog + UVM...Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. 登録 サイン・イン
