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Title: UVVM steps up a gear: A review of some of the new features in this standardized VHDL verification methodology

Description: The verification of large or complex designs targeted at FPGAs is time consuming. However, with a good testbench architecture the workload can be greatly reduced. UVVM provides an ideal VHDL testbench architecture as well as a good reuse structure. Entry-level UVVM is easy, even for beginners. For more advanced verification, the standardized verification components, the high-level software-like commands and other features will allow complex verification scenarios to be handled in a structured and understandable way. UVVM is open source and provides a ‘kick-start’ testbench with BFMs and verification components for UART, SPI, AXI-lite, AXI stream, Avalon MM, Avalon stream, I2C, GPIO, SBI, GMII and Ethernet. UVVM has been significantly updated through the ESA’s (European Space Agency’s) UVVM extension project. We have previously released the Scoreboard, and now lots of other new functionality has also been added. The most important of these new functions are Activity Watchdog, Error Injection, Monitor, Hierarchical VVCs and Specification Coverage. This presentation will provide an introduction to UVVM Utility Library, BFMs and VVCs, and then go through the new features and explain how they will help you make a better testbench and, in doing so, shorten your overall project development times. The usage of UVVM is exploding, and all the new features are already greatly appreciated by the VHDL community. UVVM is the best possible solution for all the features needed for the most efficient FPGA development and high-quality products: - The best possible Overview, Readability, Maintainability - The simplest possible control of large or complex testbenches - Unique Reusability

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