Play Webinar

Title: Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC

Description: The highly integrated Xilinx® Zynq™ UltraScale+ MPSoC architecture provides the ARM CoreSight architecture for the hardware debugging methodology. But the development process does not necessarily require hardware, and the validation process can be accelerated with unit tests or partial system tests. It needs different approaches of validation tools which can be used independently, but as important is also the co-simulation for the heterogeneous MPSoC architecture when the programmable hardware requires processor communication to the programmable logic resources such as shared memories, control logic, HDL user peripherals, DMA and interrupt handling. This webinar will give you a better understanding of using the Xilinx Vitis tool and a higher value when using Riviera-PRO simulator supporting the co-simulation. First, we will have a quick look into the Zynq UltraScale+ MPSoC architecture to better understand the necessity for simulation and emulation needs. The Xilinx Vitis tool provides a unified platform environment for multi-processing and you will see the debugging methodology for multi-core debugging. The processor system is immediately supported with the Vitis integrated QEMU but with the addition of programmable logic modules it requires the System-C based HDL models and the AXI adapters between the worlds of processing system and programmable logic. And exactly this is provided as an integrated solution when using Riviera-PRO simulator. Attendees will learn how they can improve their debugging productivity for these MPSoC architectures.

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