Play Webinar

Title: The most error prone FPGA corner cases

Description: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals. Then a typical cycle related corner case is if you read/reset the counter in the same cycle as a new event occurs – risking strange behaviour in many ways. For this simple example however, most designers will handle this correctly, - but for more complex examples – including something as simple as a UART, this type of corner case is extremely error prone. This webinar will explain these corner cases in more detail and then show why they often result in bugs, why these bugs are often not detected, and how you can detect them.

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