Play Webinar

Title: FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 4: Code, Functional and Specification Coverage

Description: Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench. Unfortunately, not many designers are applying functional coverage, and maybe part of the reason for that is the complexity surrounding previous solutions to this functionality. This presentation will show you how it works and how easy it is to get started with this new functionality in UVVM. The presentation will also explain and show the usage of Specification Coverage aka Requirement Coverage, which is a feature to track that all your specification requirements have been covered. Many of us are already familiar with Code Coverage since it’s very easy to use, but some important issues will be presented.

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