Play Webinar

Title: Using OSVVM’s AXI4 Verification Components (Part 1) Creating the AXI4 Testbench / Test Harness

Description: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having five independent interfaces: Write Address, Write Data, Write Response, Read Address, and Read Data. Going further, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. In this presentation we examine the details of the test harness including the required context references, configuring the transaction interface, configuring the AXI interface, creating clock and reset, connecting the DUT to the OSVVM AXI interface record, and connecting to the AXI VCs. We continue by examining how to size the AXI4 interface by sizing the unconstrained record elements of the AXI4 interface and OSVVM transaction interface records. We wrap up by looking at how to use AXI4 VCs inside a DUT – such as with Zynq. In this situation, the DUT does not have a port for the transaction interface(s). To address this use model, OSVVM provides another set of AXI4 VCs that use OSVVM’s virtual transaction interface (VTI). These VCs all have Vti in their name, such as Axi4ManagerVti.vhd. The Zynq subordinate interfaces (such as Axi4Memory) can share the same memory space. As a result, we look at how OSVVM configures multiple instances of the Axi4Memory to share their internal address space.

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