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このドキュメントでは、Aldec AMIの設定と起動に関する重要な情報、およびAldec HES-DVM Proto CEとBoard Compilerの使用方法を説明しています。

HES-DVM Proto CEは、アルデックのエミュレーションおよびプロトタイピングプラットフォームHES-DVMのクラウドエディションになります。 クラウドエディションは、マルチFPGAプラットフォームでデザインプロトタイプを準備するために使用される高品質のパーティショニングツールに対する需要の高まりに対応しています。 HES-DVMのクラウドエディションはプロトタイピングフローに限定されており、4つのハイエンドXilinx FPGA（Virtex UltraScale、Vitex UltraScale+、またはVirtex-7）にマッピング可能で最大4つのパーティションをサポートしています。

In this video, Farhad Fallah from Aldec company provides a deep dive into automatic multi FPGA partitioning features of HES DVM tool. You'll learn how to use HES DVM on AWS cloud to partition any ASIC design into multi FPGAs automatically which takes a lot of time for the verification engineers. Using the FPGA resources efficiently is a challenging problem in multi FPGA prototyping. The lack of enough I/O pins on FPGAs to fit today's complex SoC designs have made the prototyping process very time-consuming and costly for ASIC design companies. Making this process automated could save a lot of engineering costs for such projects.

The number of IOs used in ASIC and SoC designs are increasing almost similar to the moore's law. Because of the limitation in the number of physical IOs on FPGAs, the prototyping of more complex SoC designs that require a generous amount of IOs has become very challenging. In such cases, multiplexing is what connects the logical connections to the physical connections on the board. Doing this task manually will take time and human force. HES DVM has both user guided and automated way to do the multiplexing. In this video, Farhad Fallah from Aldec company takes you through more in-depth features that HES-DVM offers for more detailed partitioning.

In this video, Farhad Fallah from Aldec will explain how to use HES DVM board compiler tool to prepare custom board files to be used in DVM for prototyping. Board compiler is a Linux command line tool and requires the user to prepare the board file and use it as an input to the tool. Board compiler will generate a .board file which can be imported into HES DVM for prototyping purposes.

Exponential increase in the number of modules in an ASIC / SoC device has become a complex challenge for verification engineers. As it's impossible to fit a big design into a single FPGA for prototyping, multi-FPGA partitioning is in high demand. There could be specific customization for each design that requires the verification engineer to consider during the prototyping process. Being able to manually do the partitioning along with some software assisted features makes HES DVM a right choice for such tasks. In this video, Farhad Fallah from Aldec company goes over detailed features of manual partitioning using HES DVM on the AWS cloud.

In this video, you learn how to use the HES-DVM partitioning tool to prepare required files for FPGA design prototyping. HES-DVMв„ў is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins. HES-DVMв„ў provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.

Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of the multi-FPGA design setup like partitioning, multiplexing limited I/O interconnections and mapping multiple clock domains across multiple devices may cause significant delays in prototype bring-up and verification schedule. Design partitioning tool that can be used with either off-the-shelf or custom made FPGA boards will automate the most tedious tasks and so significantly reduce the risk. Aldec provides HES-DVM Proto toolbox with automatic design partitioning for multiple FPGAs including Xilinx Virtex UltraScale XCVU440. In this webinar we will demonstrate how to compile and partition an open source design of Deep Learning Accelerator into 6 FPGAs in 6 steps which are fully automated. Play webinar   

ASIC/SoCデザインのマルチFPGAによるプロトタイピングは、エミュレーション技術の中で最も高いクロックレートを実現します。しかし、プロトタイピングのためのデザインセットアップは非常に複雑で困難です。このホワイト ペーパーでは、デザインを複数の FPGA にパーティショニングする際の一般的な課題を明らかにし、プロトタイプの品質を向上させ、デザインのセットアップにかかる時間を短縮するソリューションを提供します。