Aldec Design and Verification Blog

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The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices offer a very interesting alternative of reprogrammable logic powered with the microprocessor, usually ARM. With new types of devices there is always a need for extended verification methodology. SoC ASIC has so far been the main pioneer for advanced and highly scalable verification methodologies. Due to the complexity and size of such projects, ASIC labs were actually driving EDA vendors to deliver verification solutions for their projects. With the growth of these projects, hardware emulation became a common tool which was then integrated with virtual platforms and labeled ‘hybrid co-emulation’. This hybrid solution offered a single verification platform for both software and hardware teams. Such platforms allow the performance of verification at the SoC level, allowing the entire project to be verified before the final design code is actually written and available for example, to perform the prototyping. Hybrid emulation allows the connection of the work environment of software teams using virtual platforms with the hardware engineers using emulators. Why is this so important? The issue is, until now the software portion of the project worked on the virtual models, separate from the hardware portion. Connecting these two domains allows for testing of the project at the SoC level instead of the subsystems level, which in turn increases the coverage of testing and enables the detection of problems much earlier.   Figure 1 - Hybrid co-emulation verification system.   Why is this so important for FPGAs? For a long time, it wasn’t. FPGA was the domain of hardware engineers, and software developers often didn’t even know what the FPGA was. A typical development and verification tool for FPGA was and still is an RTL simulator, even for SoC FPGA. BFM modules for interconnects like AMBA AXI were, so far, enough to bridge with the testbench. However the growth of SoC projects in FPGA size and complexity requires more. Simply stated, as FPGA projects become more complex, embedded operation systems for FPGA becomes standard, software developers start using FPGA, and there is a big demand to deliver an integrated work and verification platform for software developers and hardware engineers. This is the experience that is coming from ASIC verification methodologies. Which tools should be connected? Following the main requirement, which is to combine the software and hardware verification activities, we then need to connect a virtual platform and RTL simulator. One widely-used and well-known by software community example is QEMU, a generic and open-source machine emulator that supports various computer hardware architectures including ARM Cortex families. QEMU is used to emulate standard components like CPU subsystems and to run embedded software tests. When it comes to the RTL simulator, there are few well-known in the industry as Aldec Riviera-PRO. This solution guarantees thorough and comprehensive design verification at both the hardware and software sides without the need for dummy patches or for compromising the device driver or firmware code for an otherwise incomplete design. What does a verification flow with a virtual platform look like? The figure 2 below presents how such a flow might look and how it comperes to traditional, BFMs-only based flow. Figure 2 - QEMU Virtual Platform co-simulation with RTL simulator.   The main difference is such an environment allows the simulation of the entire SoC FPGA project instead of only the hardware. QEMU supports the processor subsystem modelling, while programmable logic is still simulated in the RTL simulator. This way the entire engineering team can work using one integrated environment and the same source code for all testing and debugging tasks. Also important, using QEMU as a testbench enables testing of the hardware with an operation system and drivers, as on the target platform. This generates much more complex and realistic test cases compared to standard testbenches, and allows debugging of detected errors before going to hardware which shortens the stage in the target board. Summary The methodology change is happening now. The complexity and multi-domain requirements of SoC projects have accelerated this change. The border between software and hardware in today’s electronics is very thin. Verification methods popular for ASIC projects are now migrating to FPGA, providing the most comprehensive development and verification work environment for all members of the project team. Table 1 compares how a verification platform can migrate from typical hardware-only simulation to virtual platform co-simulation and, as a reference, how close it is to most popular hybrid co-emulation used for ASIC designs. The verification functionality including debugging features offers the same capabilities, with the speed being a main difference limited by the RTL simulator kernel efficiency.     BFM only RTL simulation Virtual Platform and RTL simulator co-simulation Hybrid co-emulation Software engineer Not supported Supported Supported Hardware engineer Supported Supported Supported Software debug No Yes Yes Hardware debug Yes Yes Yes Speed Hz-kHz Hz-kHz MHz   Table 1.   In conclusion, due to increasing complexity of new FPGAs with embedded processors, efficient verification methodologies will be required that are capable of servicing the new features of the FPGA. The main function, from the methodology point of view, will be an integrated environment for all members of the project giving the abilities to develop, test, and debug at SoC level, not the sub-module level. FPGA is no longer a hardware domain only platform now with embedded processors and high level synthesis enabling FPGAs for the whole technology world. These elevated requirements will trigger new demands for the FPGA tools suited for the SoCs....

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator....